IMPROVEMENTS IN THE DESIGN OF THE LOW SATURATION ONSET TRANSISTOR
MOSFET saturation, saturation onset voltage, CMOS design methodology
This work presents a methodology for properly sizing the LSOT (Low Saturation Onset Transistor). The LSOT is a four-transistor network that emulates a MOS device with much lower saturation onset voltage by compensating the reverse saturation component of the main transistor drain current. The main transistor must have the same dimensions of the device to be replaced and, theoretically, the compensation device should be equal. However, the mobility degradation due to the transversal electrical field as well as other second order effects lead to current overcompensation in the structure, so that the DC output characteristic of the equivalent device presents an undesirable hump. A systematic procedure to dimension the compensation transistor is thus proposed, in order to smooth the LSOT current-voltage characteristic. A few guidelines are also suggested to dimension the other two transistors and slight modifications in the LSOT topology are tested, aiming to optimize circuit power and area. At last, we analyze the applicability of the LSOT as a succedaneum of one of the output transistors of a regulated cascode mirror. All circuits have been tested through a simulation tool.